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Monday, May 11, 2026

Unraveling the origins of the coexisting localized-interfacial mechanism in oxide-based memristors in CMOS-integrated synaptic gadget implementations


The forefront of neuromorphic analysis strives to develop units with particular properties, i.e., linear and symmetrical conductance adjustments below exterior stimuli. That is paramount for neural community accuracy when emulating a organic synapse. A parallel exploration of resistive reminiscence as a substitute for typical computing reminiscence ensues. Searching for a holistic resolution, the proposed memristive gadget on this work is uniquely poised to handle this elusive hole as a unified reminiscence resolution. Reverse biasing operations are leveraged to realize steady abrupt and gradual switching traits inside a single gadget, addressing the calls for for decrease latency and vitality consumption for binary switching purposes, and graduality for neuromorphic computing purposes. We evaluated the underlying ideas of each switching modes, attributing the anomalous gradual switching to the modulation of oxygen-deficient layers shaped between the lively electrode and oxide switching layer. The memristive cell (1R) was built-in with 40 nm transistor expertise (1T) to type a 1T–1R reminiscence cell, demonstrating a switching velocity of fifty ns with a pulse amplitude of ±2.5 V in its forward-biased mode. Making use of pulse trains of 20 ns to 490 ns within the reverse-biased mode exhibited synaptic weight properties, acquiring a nonlinearity (NL) issue of <0.5 for each potentiation and melancholy. The units in each modes additionally demonstrated an endurance of >106 cycles, and their conductance states have been additionally steady below temperature stress at 85 °C for 104 s. With the duality of the 2 switching modes, our gadget can be utilized for each reminiscence and synaptic weight-storing purposes.

Graphical abstract: Unraveling the origins of the coexisting localized-interfacial mechanism in oxide-based memristors in CMOS-integrated synaptic device implementations

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